Semiconductor storage device

ABSTRACT

According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit priority fromJapanese Patent Application No. 2012-284909, filed on Dec. 27, 2012; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storagedevice.

BACKGROUND

As examples of storage devices included in general host systems such ascomputer systems, there are magnetic hard disk drives (HDD), solid statedrives (SSD) having nonvolatile semiconductor memories such as NANDflash memory mounted thereon, and embedded NAND flash memory. SSDs andembedded NAND flash memory are classified as storages, but can also bedescribed as memory systems with extended sizes.

Such a memory system includes an interface, a first memory block, asecond memory block and a controller, for example. The first memoryblock stores data, and the second memory block is a buffer memory forwriting/reading data.

Description will be given considering an SSD as a system of the relatedart. Herein, an SSD refers to a storage constituted by NAND flash-basedsolid-state memory in a broad sense and also includes a NAND flashmemory embedded system. Since writing to NAND flash memory is performedin units of a page, there is a disadvantage that a large number of datawrite requests in smaller units (requests to write data smaller than apage size) results in many empty areas in the NAND flash memory and thusresults in decrease in the use efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram for explaining an outline of anembodiment;

FIG. 2 is a diagram illustrating an exemplary hardware configuration ofa semiconductor storage device according to a first embodiment;

FIG. 3 is a diagram illustrating an exemplary functional configurationof a device controller according to the first embodiment;

FIG. 4 is a diagram illustrating an exemplary configuration of a secondstorage unit according to the first embodiment;

FIG. 5 is a diagram illustrating an exemplary functional configurationof a memory controller according to the first embodiment;

FIG. 6 is a chart illustrating an example of control performed by awrite control unit according to the first embodiment;

FIG. 7 is a chart illustrating an example of control performed by a readcontrol unit according to the first embodiment;

FIG. 8 is a diagram illustrating an exemplary hardware configuration ofa semiconductor storage device according to a modification;

FIG. 9 is a diagram illustrating an exemplary functional configurationof a device controller according to a second embodiment;

FIG. 10 is a diagram illustrating an exemplary configuration of a secondstorage unit according to the second embodiment;

FIG. 11 is a chart illustrating an example of control performed by asecond write control unit according to the second embodiment; and

FIG. 12 is a chart illustrating an example of control performed by asearch control unit according to the first embodiment.

DETAILED DESCRIPTION

According to an embodiment, a semiconductor storage device includes afirst storage unit, a read control unit, a second storage unit, and awrite control unit. The first storage unit is configured to store datasupplied from a host device. The read control unit is configured toperform control of reading the data in accordance with a read request.The second storage unit is configured to store a logical address usedfor reading the data from the first storage unit by the read controlunit. The write control unit is configured to perform control of addingthe stored logical address to the data and write the resulting data intothe first storage unit in a case where a size of the data requested tobe written into the first storage unit by the host device is smallerthan a threshold.

An outline of an embodiment will be described before describingembodiments of the semiconductor storage device. Here, an example inwhich a first storage unit that stores data supplied from a host deviceis AND flash memory will be described. The size of metadata such as atag handled by a search memory is smaller than the page size (8 KB, forexample) of the NAND flash memory. Thus, in a case where data such as atag smaller than the page size is written in the NAND flash memory, anempty area is produced in a storage area of one page reserved in theNAND flash memory as a result of the writing.

In practice, it is known from a result of analysis of use cases of NANDflash memory in personal computers and mobile phones that small data of4 KB or smaller are frequently written. Note that, when use cases inreading and writing of data are considered, data to be written is likelyto have relationship with data previously read out. For example, a caseof opening a presentation file while a document file is open andupdating and saving the presentation file on a personal computer isassumed. Since the document file may also be read when the presentationfile is read afterward, storing data read previously in association withdata to be written allows efficient retrieval of the association whenthe written data is read out.

A significant difference based on an essential difference betweenmemories such as NAND flash memory from/to which reading/writing isperformed in units of pages and other memories is that, even NAND flashmemory is suitable for increasing the capacity, the capacity may not bemade use of depending on use cases because writing is performed in unitsof pages.

In view of the aforementioned circumstances, a feature of the embodimentis that writing as much information that will be valuable when readingas possible in empty areas of pages is found to be useful in increasingthe speed of a memory system in practical use. As illustrated in FIG. 1,according to the embodiment, in a case where the size of data requestedto be written into NAND flash memory (hereinafter may be referred to as“data to be written”) is smaller than a page size representing the unitsize for writing (more specifically, in a case where the proportion ofdata to be written in a page is smaller than a threshold (50%, forexample), an address last stored in a buffer memory (corresponding to a“second storage unit” in the claims) that is not illustrated and inwhich the history of addresses used for reading data is read out fromthe buffer memory and added to the data to be written so that there willbe no empty area in the area other than a redundant part of the page.Then, predetermined redundant information (such as a logical addressspecified by a host device for the data requested, an ECC, a parity, andthe number of addresses) is appended into the redundant part of thepage, and the page is written into the NAND flash memory.

When reading of the data written in the NAND flash memory is requestedafterward, the address added in writing is also read out together withthe written data. As a result of reading out data associated with theread address from the NAND flash memory and holding the data in thebuffer memory (that is, performing look-ahead), the data read ahead canbe transmitted to the host device without accessing the NAND flashmemory when reading of the data is request, which allows efficientreading of data strongly correlated with the written data.

Embodiments of the semiconductor storage device will be described belowin detail with reference to the accompanying drawings.

First Embodiment

FIG. 2 is a block diagram illustrating an example of hardwareconfigurations of a device 100 that is a semiconductor storage deviceand a host device 200 according to a first embodiment. As illustrated inFIG. 2, the host device 200 includes a CPU 201, a main memory 202, andan interface unit 203 to connect to the device 100, which are connectedwith one another via a bus 204.

The device 100 includes a controller chip 110 and a first storage unit120. The controller chip 110 includes a host interface unit 111, adevice controller 112, a second storage unit 113, and a memorycontroller 114, which are connected to one another via a bus 115. In thedevice 100, a high-speed and efficient bus line arrangement isdesirable. In the meantime, two or more types of bus lines may be usedin the device 100 depending upon a difference between interfacestandards and external interface standards, for example.

Furthermore, in the example of FIG. 1, the first storage unit 120 isconnected to the controller chip 110 via the memory controller 114. Thefirst storage unit 120 is a device capable of storing data supplied fromthe host device 200 (from a different perspective, data to be used bythe host device 200). In the present embodiment, the first storage unit120 is a NAND flash memory, but is not limited thereto. Alternatively,the first storage unit 120 may be constituted by a plurality of chips soas to increase the storage capacity. The first storage unit 120 is notlimited to the above, and any storage medium can be applied thereto aslong as it is a semiconductor memory having memory nonvolatility.Examples of the first storage unit 120 include nonvolatile memories suchas an MRAM (magnetoresistive random access memory), an ReRAM (resistancerandom access memory), an FeRAM (ferroelectric random access memory),and a PCRAM (phase-change random access memory).

The host device 200 (the interface unit 203) is connected to the hostinterface unit 111 of the device 100 via an external bus 300 such as anAMBA (advanced microcontroller bus architecture). For example, the hostinterface unit 111 is appropriately selected from an SATA (serialadvanced technology attachment), a PCI Express, an eMMC (embedded MMC),a UFS ((universal flash storage)), a USB (universal serial bus) and thelike.

The host interface unit 111 can receive requests from the host device200, which is a host device of the device 100. For example, the hostinterface unit 111 can receive a write request requesting to write datainto the first storage unit 120 and a read request requesting to readdata from the first storage unit 120 from the host device 200. In thisexample, a write request contains information requesting execution ofwriting, data requested to be written, and a logical address indicatingthe place to which the data requested to be written is assigned amongvirtual space addresses in a program. A read request containsinformation requesting execution of reading, and a logical addressindicating the place to which data requested to be read is assignedamong virtual space addresses in a program. The logical address isspecified by the host device 200.

The device controller 112 is a control device configured to controlwriting of data into the first storage unit 120 and reading of data fromthe first storage unit 120 in response to a request from the host device200 received by the host interface unit 111. Detailed functions of thedevice controller 112 will be described later.

The second storage unit 113 is a memory smaller than the first storageunit 120 but higher in resistance to rewrite/read than the first storageunit 120. The second storage unit 113 has a work area for storingvarious computation results of the device controller 112 and the memorycontroller 114 to be described later. The second storage unit 113 alsohas an area for storing the history of logical addresses used forreading data (the history of logical addresses associated with readdata). Details of the second storage unit 113 will be described later.The second storage unit 113 may be nonvolatile so that data stored inthe second storage unit 113 will not be lost even when power is cut off.For example, when the first storage unit 120 is a NAND flash memory, thesecond storage unit 113 can be an MRAM, a PCRAM, an ReRAM, an FeRAM orthe like.

The memory controller 114 is a hardware module having functions ofwriting data supplied from the host device 200 into the first storageunit 120 and reading data stored in the first storage unit 120 under thecontrol by the device controller 112. Detailed functions of the memorycontroller 114 will be described later.

Next, detailed functions of the device controller 112 will be described.FIG. 3 is a block diagram illustrating an exemplary functionalconfiguration of the device controller 112. As illustrated in FIG. 3,the device controller 112 includes a receiving unit 101, a write controlunit 102, and a read control unit 103. The receiving unit 101 receivesrequests from the host device 200.

When a write request is received by the receiving unit 101, the writecontrol unit 102 performs control (may also be referred to as “writecontrol”) of writing information containing data requested to be written(data contained in the write request; hereinafter may also be referredas “data to be written”) into the first storage unit 120. As will bedescribed later, information on which write control is to be performedmay contain a logical address added to the data to be written inaddition to the predetermined redundant information. In the presentembodiment, the write control unit 102 generates a write commandinstructing to perform writing, adds information (information on whichwrite control is to be performed) containing data to be written and aphysical address indicating an area in the first storage unit 120 wherethe data to be written is to be written to the generated write command,and transmits the write command to the memory controller 114. Note thatwriting of the information including data and redundant information intothe first storage unit 120 is performed in ascending order of pagesregardless of the logical addresses.

In a case where the size of the data to be written is smaller than athreshold, the write control unit 102 performs control of adding thelogical address (the logical address used for reading data) stored inthe second storage unit 113 to the data to be written and write theresulting data into the first storage unit 120. More specifically, in acase where the size of the data to be written is smaller than the pagesize representing the unit for writing, the write control unit 102performs control of adding the logical address stored in the secondstorage unit 113 to the data to be written and write the resulting datainto the first storage unit 120. Still more specifically, in a casewhere the proportion of the data to be written in a page (the proportionof the data to be written with respect to the page size) is smaller than50%, the write control unit 102 performs control of adding the logicaladdress stored in the second storage unit 113 to the data to be writtenso that there will be no empty area other than the area for theredundant part in the page, append at least an offset representinginformation allowing the length of the data to be written to be obtainedinto the redundant part, and write the resulting data into the firststorage unit 120. In this case, the information on which write controlis to be performed includes the data to be written having a size smallerthan the threshold, the logical address added to the data to be written,and the redundant information (at least containing an offset) describedin the redundant part.

Furthermore, the write control unit 102 performs control of updatinglogical-to-physical translation information indicating an associationbetween the logical address specified by the host device 200 and thephysical address indicating the position in the first storage unit 120each time the write control unit 102 performs the write control. Morespecifically, the write control unit 102 performs control of newlyadding the logical address contained in the write request received fromthe host device 200 and the physical address indicating the position(area) in the first storage unit 120 into which the data to be writtenis written in association with each other to the logical-to-physicaltranslation information each time the write control unit 102 performsthe write control. In this example, the logical-to-physical translationinformation has a data structure in a form of a table and the bodythereof is stored in the first storage unit 120. For performinglogical-to-physical translation, the logical-to-physical translationinformation is read into the second storage unit 113 and used. In thefollowing description, the logical-to-physical translation informationin the present embodiment will be referred to as a “logical-to-physicaltranslation table” (may also be referred to as an “L2P table”). In thepresent embodiment, the content of the logical-to-physical translationtable is updated each time write control is performed by the writecontrol unit 102.

Next, functions of the read control unit 103 will be described. When aread request is received by the receiving unit 101, the read controlunit 103 performs control (hereinafter may also referred to as “firstread control”) of referring to the logical-to-physical translation tableto identify the physical address associated with the logical addresscontained in the read request (performs logical-to-physicaltranslation), and control of reading out information stored in thelocation indicated by the identified physical address. In the presentembodiment, the read control unit 103 generates a read command toinstruct the memory controller 114 to perform reading, adds the physicaladdress obtained by the logical-to-physical translation to the generatedread command, and transmits the read command to the memory controller114. Then, the read control unit 103 can receive the information readout from the first storage unit 120 by the memory controller 114 as aresponse to the read command.

When a logical address added to the data by the write control unit 102is contained in the information read according to the first readcontrol, the read control unit 103 refers to the logical-to-physicaltranslation table to identify the physical address associated with thelogical address added to the data by the write control unit 102. In thepresent embodiment, the read control unit 103 refers to the offsetcontained in the information read according to the first read control,and obtains the logical address added to the data in writing from partof the read information other than the data and the redundant part if itis determined that the data length is smaller than the threshold (inthis example, if it is determined that the proportion of the data lengthwith respect to the page is smaller than 50%). The read control unit 103then refers to the logical-to-physical translation table to identify thephysical address associated with the obtained logical address.

The read control unit 103 performs control (hereinafter may alsoreferred to as “second read control”) of reading information stored atthe position in the first storage unit 120 indicated by the physicaladdress identified as described above. In the present embodiment, theread control unit 103 generates a read command to instruct the memorycontroller 114 to perform reading, adds the physical address identifiedas described above to the generated read command, and transmits the readcommand to the memory controller 114. The read control unit 103 canreceive the information read out from the first storage unit 120 by thememory controller 114 as a response to the read command. The readcontrol unit 103 then performs control of storing the data contained inthe information read out according to the second read control and thelogical address in association with each other into the second storageunit 113.

Accordingly, a physical address used for second read control and dataare stored in association with each other into the second storage unit113 each time the second read control is performed. In the followingdescription, a combination of a logical address used in second readcontrol and data associated with the logical address stored in thesecond storage unit 113 may be referred to as cache data.

When a logical address matching the logical address contained in theread request received by the receiving unit 101 and data are stored inassociation with each other in the second storage unit 113, the readcontrol unit 103 performs third read control of reading the dataassociated with the logical address matching the logical addresscontained in the read request from the second storage unit 113. In otherwords, when there is cache data containing a logical address matchingthe logical address contained in the read request is present among oneor more cache data stored in the second storage unit 113, the readcontrol unit 103 performs control of reading data contained in the cachedata. In this case, the read control unit 103 need not perform controlof reading out data from the first storage unit 120, which can increasethe reading speed.

Furthermore, each time the read control unit 103 performs first readcontrol, the read control unit 103 at least performs control of storingthe logical address used in first read control into the second storageunit 113. For example, the read control unit 103 can also store thelogical address used in the first read control and the data readaccording to the first read control in association with each other within the capacity of the second storage unit 113 (for example, a thirdstorage unit 130, which will be described later).

Furthermore, when storing a logical address used in the first readcontrol or the second read control into the second storage unit 113, theread control unit 103 also stores time information indicating the timeat which the information is read from the first storage unit 120 inassociation therewith. Accordingly, in the present embodiment, thesecond storage unit 113 stores time information indicating the time atwhich reading is performed (the time at which the first read control orthe second read control is performed) in association with each logicaladdress used in the first read control or the second read control. Morespecific details of the second storage unit 113 will be described later.

In a case where the size of the data to be written is smaller than athreshold, the aforementioned write control unit 102 selects a logicaladdress used for reading within a predetermined time period by the readcontrol unit 103 before writing of the data to be written is requested(before the write request is received) from among logical addressesstored in the second storage unit 113 and adds the selected logicaladdress to the data to be written. More specifically, in a case wherethe size of the data to be written is smaller than the threshold, thewrite control unit 102 selects a logical address associated with timeinformation indicating time contained in the predetermined time periodfrom among the logical addresses stored in the second storage unit 113and adds the selected logical address to the data to be written.

More specific details are as follows. In the present embodiment, asillustrated in FIG. 4, the second storage unit 113 includes the thirdstorage unit 130 and a fourth storage unit 140. The third storage unit130 stores time information indicating the time at which reading isperformed according to the first read control in association with eachlogical address used in the first read control. The fourth storage unit140 stores data read according to the second read control and timeinformation indicating the time at which reading is performed accordingto the second read control in association with each logical address usedin the second read control. In a case where the size of the data to bewritten is smaller than the threshold, the write control unit 102 thenselects a logical address (which may be a logical address used in thefirst read control or a logical address used in the second read control)associated with time information indicating time within thepredetermined time period from among logical addresses stored in thethird storage unit 130 and the fourth storage unit 140 and adds theselected logical address to the data to be written.

Note that the predetermined time period may be set to any time periodsuch as a time period from a time point that is a preset time before awrite request point representing the time point at which a write requestfrom the host device 200 is received by the receiving unit 101 to thewrite request point.

In addition, the length of the predetermined time period may be set toany length. For example, however, even if the history of logicaladdresses used for reading after the power of the device 100 is turnedon is saved and a logical address used for reading long before writingthe data to be written (data requested to be written) smaller than thepage size is added to the data to be written and written therewith, thecorrelation therebetween may be too small to produce sufficient effectsof look-ahead. As a specific example, in a case of smart phones, sincethe time during which a smart phone is used in a day is, statistically,most often 50 minutes or shorter, it can be deemed that data read at aninterval of 50 minutes or shorter before writing (a write request timepoint, for example) is strongly correlated with the data to be written.Accordingly, if a logical address associated with the data read at aninterval of 50 minutes or shorter before writing is added to the data tobe written and written therewith, data strongly correlated with the datato be written can be efficiently read out. In a case of PCs, forexample, since the time during which a PC is used in a day is,statistically, shorter than three hours in the majority of cases, if alogical address associated with data at an interval shorter than threehours is added to the data to be written smaller than the page sized andwritten therewith, data strongly correlated with the data to be writtencan be efficiently read out.

In addition, for example, each time the write control performs writecontrol, the write control unit 102 can perform control of storing alogical address contained in a write request and time informationindicating the time at which the writing according to the write controlin association with each other into the third storage unit 130. In thiscase, a time period from a time point when previous writing is performed(a time point when a previous write request is received by the receivingunit 101, for example) to a time point when the latest writing isperformed can be set as the predetermined time period.

In the present embodiment, the device controller 112 includes a CPU orthe like, for example, and the functions of the receiving unit 101, thewrite control unit 102, and the read control unit 103 are realized byexecuting programs stored in a ROM or the like, which is notillustrated, by the CPU. Alternatively, for example, at least some ofthe receiving unit 101, the write control unit 102, and the read controlunit 103 may be realized by dedicated hardware circuits.

Next, the functions of the memory controller 114 will be described. FIG.5 is a block diagram illustrating an exemplary functional configurationof the memory controller 114. As illustrated in FIG. 5, the memorycontroller 114 includes a command receiving unit 104, a correcting unit105, a writing unit 106, and a reading unit 107.

The command receiving unit 104 receives a command (a write command or aread command) transmitted from the device controller 112. The correctingunit 105 performs an encoding process on information added to a writecommand received by the command receiving unit 104 (information on whichwrite control is to be performed by the write control unit 102). In thisexample, the correcting unit 105 performs a process of adding redundantinformation (called parity when the parity of data bits is utilized) forperforming an error correction process (ECC process) of bits on theinformation to be written into the first storage unit 120. Thecorrecting unit 105 also performs an error correction process (ECCprocess) on information read out from the first storage unit 120 by thereading unit 107, which will be described later. Herein, the secondstorage unit 113 further has a work area for the encoding processperformed by the correcting unit 105. The second storage unit 113further has a work area for the error correction process performed bythe correcting unit 105. Thus, the second storage unit 113 alsofunctions as a working memory for the encoding process and the errorcorrection process performed by the correcting unit 105.

The writing unit 106 writes the information into the first storage unit120 according to the write command received by the command receivingunit 104. More specifically, the writing unit 106 write informationencoded by the correcting unit 105 into an area in the first storageunit 120 indicated by a physical address added to the write command. Thereading unit 107 reads out information from the first storage unit 120according to a read command received by the command receiving unit 104.More specifically, the reading unit 107 reads out information stored inan area in the first storage unit 120 indicated by a physical addressadded to the read command. The information read out by the reading unit107 is decoded through an error correction process performed by thecorrecting unit 105, and the decoded information is transmitted to thedevice controller 112 (the read control unit 103) as a response to theread command.

In the present embodiment, the memory controller 114 is a hardwaremodule and the command receiving unit 104, the correcting unit 105, thewriting unit 106, and the reading unit 107 are realized by dedicatedhardware circuits. Alternatively, for example, the memory controller 114may include a CPU or the like, and at least some functions of thecommand receiving unit 104, the correcting unit 105, the writing unit106, and the reading unit 107 may be realized by executing programsstored in a ROM or the like, which is not illustrated, by the CPU.

Next, an example of control performed by the write control unit 102described above will be described with reference to FIG. 6. FIG. 6 is aflowchart illustrating an example of the control performed by the writecontrol unit 102. In this example, description will be made on theassumption that a write request from the host device 200 is received bythe receiving unit 101. As illustrated in FIG. 6, the write control unit102 checks whether or not the size of data (data to be written)contained in the write request is smaller than the threshold (step S1).In the present embodiment, the write control unit 102 checks whether ornot the proportion of the data to be written in a page is smaller than50% as described above. If it is determined that the size of the data tobe written is equal to or larger than the threshold (step S1: NO), theprocess proceeds to step S6, which will be described later.

If it is determine in step S1 that the size of the data to be written issmaller than the threshold (step S1: YES), the write control unit 102calculates the size of the empty area (step S2). Subsequently, the writecontrol unit 102 checks whether or not the calculated size of the emptyarea is equal to or larger than a threshold (step S3). This threshold isset to a value allowing determination on whether or not the size of anempty area is equal to or larger than the size of at least one logicaladdress. If it is determined that the calculated size of the empty areais smaller than the threshold (step S3: NO), the process proceeds tostep S6, which will be described later.

If, on the other hand, it is determined that the calculated size of theempty area is equal to or larger than the threshold (step S3: YES), thewrite control unit 102 obtains (selects) a logical address associatedwith time information indicating time within the predetermined timeperiod from among logical addresses stored in the second storage unit113 (step S4). In the present embodiment, the write control unit 102selects logical addresses each associated with time informationindicating time within the predetermined time period from among logicaladdress stored in the third storage unit 130 and the fourth storage unit140 sequentially from the logical address associated with the earliesttime within the calculated size of the empty area.

Subsequently, the write control unit 102 adds one or more logicaladdresses selected in step S4 to the data to be written (step S5).Subsequently, the write control unit 102 appends a logical addresscontained in the write request received by the receiving unit 101 and anoffset allowing the data length of the data to be written to be obtainedinto the redundant part representing an area for redundant data in thepage size that is the unit for writing (step S6). Subsequently, thewrite control unit 102 generates a write command instructing the memorycontroller 114 to perform writing, adds information on which writecontrol is to be performed and a physical address indicating theposition in the first storage unit 120 at which the data to be writtenis to be written to the generated write command, and transmits the writecommand to the memory controller 114 (step S7). The memory controller114 in receipt of the write command from the write control unit 102 thenwrites the information into the first storage unit 120 according to thereceived write command. When writing according to the received writecommand is completed, the memory controller 114 transmits notificationinformation informing that writing is completed as a response to thewrite command to the write control unit 102. This allows the writecontrol unit 102 to know that the writing is completed.

Subsequently, the write control unit 102 updates the logical-to-physicaltranslation table (L2P table) (step S8). As described above, in thepresent embodiment, the write control unit 102 performs control of newlyadding the logical address contained in the write request received bythe receiving unit 101 and the physical address indicating the positionin the first storage unit 120 at which the data to be written is writtenin association with each other into the logical-to-physical translationtable.

Next, an example of control performed by the read control unit 103described above will be described with reference to FIG. 7. FIG. 7 is aflowchart illustrating an example of the control performed by the readcontrol unit 103. In this example, description will be made on theassumption that a read request from the host device 200 is received bythe receiving unit 101. As illustrated in FIG. 7, the read control unit103 first checks whether or not a logical address matching the logicaladdress contained in the read request and data are stored in associationwith each other in the second storage unit 113 (step S10). In thepresent embodiment, the read control unit 103 checks whether or notcache data containing the logical address contained in the read requestis stored in the fourth storage unit 140 as described above.

If it is determined in step S10 that a logical address matching thelogical address contained in the read request and data are stored inassociation with each other in the second storage unit 113 (step S10:YES), that is, if it is determined that cache data containing thelogical address contained in the read request is present, the readcontrol unit 103 reads out the data associated with the logical addressmatching the logical address contained in the read request from thesecond storage unit 113, and transmits the read data as a response tothe read request to the host device 200 (step S11). The processing instep S11 corresponds to the third read control. If, on the other hand,it is determined in step S10 that a logical address matching the logicaladdress contained in the read request and data are not stored inassociation with each other in the second storage unit 113 (step S10:NO), that is, if it is determined that cache data containing the logicaladdress contained in the read request is not present, the processproceeds to step S12.

In step S12, the read control unit 103 refers to the logical-to-physicaltranslation table to identify the physical address associated with thelogical address contained in the read request (step S12). Subsequently,the read control unit 103 generates a read command to instruct thememory controller 114 to perform reading, adds the physical addressidentified in step S12 to the generated read command, and transmits theread command to the memory controller 114 (step S13). The memorycontroller 114 in receipt of the read command reads out information fromthe first storage unit 120 and transmits the read information to theread control unit 103 according to the received read command. Thus, theread control unit 103 receives the information read out by the memorycontroller 114 as a response to the read command (step S14).

The processing in steps S12 to S14 corresponds to the first readcontrol. Subsequently, the read control unit 103 refers to the offsetcontained in the information read out according to the first readcontrol of checking whether or not the data length is smaller than thethreshold (step S15). In the present embodiment, the read control unit103 checks whether or not the proportion of the data length in a page issmaller than 50% as described above. If it is determined that the datalength is equal to or larger than the threshold (step S15: NO), the readcontrol unit 103 transmits data contained in the information read outaccording to the first read control as a response to the read request tothe host device 200 (step S16).

If, on the other hand, it is determined in step S15 that the data lengthis smaller than the threshold (step S15: YES), the read control unit 103obtains a logical address added to the data in writing from the partother than the data and the redundant part of the information read outaccording to the first read control (step S17). In the presentembodiment, the read control unit 103 may also transmit data smallerthan the threshold contained in the information read out according tothe first read control as a response to the read request to the hostdevice 200 in parallel with the processing in step S17. Note that thetiming at which the data smaller than the threshold contained in theinformation read out according to the first read control is transmittedto the host device 200 can be alternatively changed to any timing.

Subsequently, the read control unit 103 refers to thelogical-to-physical translation table to identify a physical addressassociated with each of the one or more logical addresses obtained instep S17 (step S18). Subsequently, the read control unit 103 generates aread command to instruct the memory controller 114 to perform reading,adds the physical address identified in step S18 to the generated readcommand, and transmits the read command to the memory controller 114(step S19). The memory controller 114 in receipt of the read commandreads out information from the first storage unit 120 and transmits theread information to the read control unit 103 according to the receivedread command. Thus, the read control unit 103 receives the informationread out by the memory controller 114 as a response to the read command(step S20).

The processing in steps S17 to S20 corresponds to the second readcontrol. After step S20, the read control unit 103 performs control ofstoring the data contained in the information received by the memorycontroller 114 (the information read out according to the second readcontrol) and the logical address in association with each other into thesecond storage unit 113 (the fourth storage unit 140) (step S21). As aresult, cache data read ahead is newly added to the fourth storage unit140.

According to the present embodiment, since the logical address used forreading (the logical address associated with read data) is added to thedata to be written and written therewith into the first storage unit 120in a case where the size of the data to be written is smaller than thethreshold as described above, it is possible to prevent a wasteful emptyarea from being produced in the first storage unit 120 to which the datais written.

In the present embodiment, a logical address used for reading within apredetermined time period before the time at which writing of data to bewritten is requested is employed as the logical address to be added tothe data to be written smaller than the threshold. Then, when reading ofthe written data smaller than the threshold is requested after the datais written into the first storage unit 120, the logical address added inwriting is also read out together with the written data. Since dataassociated with the read logical address is then read out (read ahead)from the first storage unit 120 and held in the second storage unit 113as cache data associated with the logical address, when there is arequest for reading data read ahead, it is possible to transmit the datato the host device 200 without accessing to the first storage unit 120.Thus, according to the present embodiment, it is possible to produce anadvantageous effect that data strongly correlated with written data canbe efficiently read out while preventing a wasteful empty area to beproduced in the first storage unit 120.

Modification 1 of First Embodiment

A mode in which a logical address contained in cache data read ahead,for example, is not added to data to be written smaller than thethreshold may be applied. In this case, since the fourth storage unit140 need not hold time information, the fourth storage unit 140 onlyneeds to store the logical address used in the second read control anddata read out according to the second read control in association witheach other. In a case where the size of the data to be written issmaller than the threshold, the write control unit 102 then performscontrol of selecting a logical address associated with time informationindicating time within the predetermined time period from among logicaladdresses stored in the third storage unit 130 and add the selectedlogical address to the data to be written.

Modification 2 of First Embodiment

The third storage unit 130 may be a FIFO (first-in-first-out) memory,for example. Thus, when the storage amount of logical addresses exceedsthe capacity of the third storage unit 130, the logical addresses aredeleted sequentially from the oldest one.

Modification 3 of First Embodiment

A mode in which a buffer memory 150 is provided separately from thesecond storage unit 113 (separately from the controller chip 110) asillustrated in FIG. 8 may be applied so as to reserve a sufficientworking area for storing various computation results from the devicecontroller 112 and the memory controller 114, for example. In theexample of FIG. 8, the buffer memory 150 is connected to the bus 115 inthe controller chip 110. When the second storage unit 113 is an SRAM andthe buffer memory 150 is a DRAM, for example, the logical-to-physicaltranslation table stored in the first storage unit 120 may betemporarily transferred to the buffer memory 150 and part thereof maythen be transferred to the second storage unit 113 for use since theaccess speed (reading/writing speed) of the SRAM is higher than that ofthe DRAM.

Second Embodiment

Next, a second embodiment will be described. Parts that are the same asthose in the first embodiment described above will be designated by thesame reference numerals and description thereof will not be repeated asappropriate. A semiconductor storage device according to the secondembodiment has a search function in addition to the write/read functionsdescribed in the first embodiment. The search scheme and method will bedescribed below before description of the semiconductor storage deviceaccording to the second embodiment.

For effectively retrieving data such as a text associated with anothertext, a specific bit pattern in a binary file, a specific pattern in avideo file and a distinctive audio pattern in an audio file that arestored in a semiconductor storage device, a data read functionspecifying data is desired. Accordingly, a method of storing data withmetadata associated therewith in advance and referring to the metadataso as to obtain desired data is used. One method for managing metadatais a key-value store (KVS) in which data have one-to-one or one-to-manyrelationships. In the KVS, when a key is supplied as a search request, avalue associated therewith is then output.

The semiconductor storage device in the second embodiment processes KVSdata (key-value information) efficiently and at a high speed by using anaddress translation table. This address translation table is referred toas a K2P table that is a translation table between fixed-lengthaddresses (key addresses) obtained from keys and physical addresses. Aspecific example of processing for retrieving KVS data will be describedbelow. In general, the KVS refers to a database management technique inwhich sets of keys and values are written allowing a value to be readout by specifying a key. In general, the KVS is often used over anetwork. The storage of data is inevitably a certain local memory or acertain storage system.

Data is usually read by specifying the top address of the memory inwhich the data is stored and the data length. Data addresses are managedin units of a 512-byte sector, for example, by an OS or a file system ofthe host system. Alternatively, if the file system need not be limited,data addresses may be managed in units of 4-KB or 8-KB in conformitywith the read/write page size of the NAND flash memory, for example.

The simplest search procedures are as the following (1) to (3).

(1) Convert a key to fixed-length data by a hash function or the likeand translate the fixed-length data to an address of an available memoryto obtain a fixed-length address. Set the fixed-length address resultingfrom the translation to a key address.(2) Refer to a K2P table saved in NAND flash memory to obtain a physicaladdress.(3) Read data at the physical address and output the read data tooutside of the memory system.

Such relationships between real data addresses and KVS data andrelationships between keys and values correspond to relationshipsbetween elements and sets. Specifically, in a typical file, when a filewith a file name of “a-file.txt” is a set and there is text data of“This is a book” in the file, for example, each word thereof is anelement.

In the case of key/value, when placed in a metadata address space, therelationships between sets and elements are reversed and rearranged.That is, the relationships may be converted to “inverted” relationshipsand saved. For example, in a set of “book”, file names of “a-file.txt”and “b-file.txt” are saved as elements. In the case of key/value, therearranged set name (“book”) is searched for and elements (“a-file.txt”,“b-file.txt”) thereof are requested. These are practically procedures ofcreation of inverted files and search typically performed in full-textsearch, which can be said to be one practical example of key/value.

For manufacturing a searcher and storage in the KVS method using K2P asdescribed above, it is desirable to provide a nonvolatile buffer memoryfor storage in response to a search request. Furthermore, since the K2Ptable is read out from the NAND flash memory and expanded in the buffermemory, the buffer memory is desirably nonvolatile so as to be ready forsudden power cut-off. In practice, it is rare that the number of searchrequests is one but a plurality of search results are processed in adevice. It is thus desirable to provide a high-speed nonvolatile buffermemory for efficiently performing search operation, that is, setoperation such as AND, OR, and NOT. Since a search request mustcertainly be saved in the nonvolatile buffer until data processing iscompleted, a nonvolatile memory having long-term reliability isdesirable.

Specific details of the semiconductor storage device according to thesecond embodiment will be described below. Since the basic configurationis similar to that of the device 100 according to the first embodiment,the part relating to the search function will mainly be described.

FIG. 9 is a block diagram illustrating an exemplary functionalconfiguration of a device controller 210 according to the secondembodiment, in which only the part relating to the search function isillustrated. As illustrated in FIG. 9, the device controller 210includes a receiving unit 211, a second write control unit 212, and asearch control unit 213. In this example, the second write control unit212 corresponds to a “write control unit” in claim 11.

A second storage unit 220 of the second embodiment stores a key addressused for searching for data associated with a key specified by the hostdevice 200 from among data stored in the first storage unit 120. Detailsof the second storage unit 220 will be described later.

A memory controller 250 according to the second embodiment performswriting and reading of information into and from the first storage unit120 under the control of the device controller 210 similarly to thefirst embodiment. Since the functions of the memory controller 250 aresubstantially the same as in the first embodiment, detailed descriptionthereof will not be repeated here.

Referring back to FIG. 9, description will be made on the functions ofthe device controller 210. The receiving unit 211 receives requests fromthe host device 200. Here, the receiving unit 211 receives a key-valuewrite request requesting to write a combination of data and a keyrepresenting metadata associated with the data, a search requestrequesting to search for data associated with a specified key, a setoperation condition for narrowing search results, and the like. Akey-value write request contains information requesting to performwriting and a combination of key and data (a set of key-value), and asearch request contains information requesting to perform a search and akey specified by the host device 200.

Next, functions of the second write control unit 212 will be described.When a key-value write request is received by the receiving unit 211,the second write control unit 212 hashes a key contained in thekey-value write request to convert the key into a key address made offixed-length data. The second write control unit 212 then performscontrol (hereinafter may be referred to as “second write control”) ofwriting information containing data (hereinafter may be referred to as“value data to be written”) contained in the key-value write requestinto the first storage unit 120. As will be described later, informationon which second write control is to be performed may contain a keyaddress added to the value data to be written in addition topredetermined redundant information. In the second embodiment, thesecond write control unit 212 generates a write command instructing toperform writing, adds information (information on which second writecontrol is to be performed) containing value data to be written and aphysical address indicating an area in the first storage unit 120 wherethe value data to be written is to be written to the generated writecommand, and transmits the write command to the memory controller 250.

In a case where the size of the value data to be written is smaller thana threshold, the second write control unit 212 performs control ofadding a key address stored in the second storage unit 220 (a keyaddress used for searching for data related to the key specified by thehost device 200) to the value data to be written and write the resultingvalue data into the first storage unit 120. In the second embodiment, ina case where the proportion of the value data to be written in a page issmaller than 50%, the second write control unit 212 performs control ofadding the key address stored in the second storage unit 220 to thevalue data to be written so that there will be no empty area other thanthe area for the redundant part in the page, append at least an offsetrepresenting information allowing the length of the value data to bewritten to be obtained into the redundant part, and write the resultingdata into the first storage unit 120. In this case, the information onwhich the second write control is to be performed includes the valuedata to be written having a size smaller than the threshold, the keyaddress added to the value data to be written, and the redundantinformation (at least containing an offset) described in the redundantpart.

Furthermore, the second write control unit 212 performs control ofupdating address translation information (hereinafter may also referredto as a “K2P table”) indicating an association between a key addressobtained by converting a key specified by the host device 200 and aphysical address indicating a position in the first storage unit 120each time the second write control unit 212 performs the second writecontrol. More specifically, the second write control unit 212 performscontrol of newly adding the key address obtained by converting the keycontained in the key-value write request received from the host device200 and the physical address indicating the position in the firststorage unit 120 into which the value data to be written is written inassociation with each other to the K2P table each time the second writecontrol unit 212 performs the second write control. In this example, thebody of the K2P table is stored in the first storage unit 120. Forperforming address translation (K2P translation), the K2P table is readinto the second storage unit 220 and used. The content of the K2P tableis updated each time the second write control is performed by the secondwrite control unit 212.

Next, functions of the search control unit 213 will be described. When asearch request is received by the receiving unit 211, the search controlunit 213 hashes a key contained in the search request to convert the keyinto a key address made of fixed-length data. The search control unit213 then performs control (hereinafter may be referred to as “firstsearch control”) of referring to the K2P table to identify a physicaladdress associated with the key address (performs K2P translation), andcontrol of reading out information stored at the position indicated bythe identified physical address. In the present embodiment, the searchcontrol unit 213 generates a search command to instruct the memorycontroller 250 to perform a search, adds the physical address obtainedby the K2P translation to the generated search command, and transmitsthe search command to the memory controller 250. Then, the searchcontrol unit 213 can receive the information read out from the firststorage unit 120 by the memory controller 250 as a response to thesearch command.

When a set operation condition is received together with a plurality ofsearch requests from the host device 200, for example, the searchcontrol unit 213 may perform set operation on a set of data contained inthe information read out from the first storage unit 120 by using thekey addresses obtained by converting keys in the respective searchrequests according to the received set operation condition to narrow thesearch results. Note that a mode in which this function of performingset operation is implemented by the memory controller 250 instead of thedevice controller 210 may be applied, for example.

When a key address added to data by the second write control unit 212 iscontained in the information read out according to the first searchcontrol, the search control unit 213 refers to the K2P table to identifythe physical address associated with the key address added to the databy the second write control unit 212. In the present embodiment, thesearch control unit 213 refers to the offset contained in theinformation read out according to the first search control, and obtainsthe key address added to the data in writing from the part other thanthe data and the redundant part of the information read out according tothe first search control if it is determined that the data length issmaller than the threshold. The search control unit 213 then refers tothe K2P table to identify the physical address associated with theobtained key address.

The search control unit 213 performs control (hereinafter may bereferred to as “second search control”) of reading out informationstored at a position in the first storage unit 120 indicated by thephysical address identified as described above. In the presentembodiment, the search control unit 213 generates a search command toinstruct the memory controller 250 to perform a search, adds thephysical address identified as described above to the generated searchcommand, and transmits the search command to the memory controller 250.The search control unit 213 can receive the information read out fromthe first storage unit 120 by the memory controller 250 as a response tothe search command. The search control unit 213 then performs control ofstoring the data contained in the information read out according to thesecond search control described above and the key address in associationwith each other into the second storage unit 220.

Accordingly, each time the second search control is performed, searchcache data containing a key address used for the second search controland data in association with each other is stored into the secondstorage unit 220.

When search cache data containing a key address matching the key addressobtained by converting the key contained in the search request receivedby the receiving unit 211 is present in the second storage unit 220, thesearch control unit 213 performs control of reading out data containedin the search cache data containing the key address obtained byconverting the key contained in the search request. In this case, thesearch control unit 213 need not perform control of reading out datafrom the first storage unit 120, which can increase the reading speed.

Furthermore, each time the search control unit 213 performs the firstsearch control, the search control unit 213 at least performs control ofstoring the key address used in first search control into the secondstorage unit 220.

Furthermore, when storing a key address used in the first search controlor the second search control into the second storage unit 220, thesearch control unit 213 also stores time information indicating the timeat which the information is read from the first storage unit 120 inassociation therewith. Accordingly, the second storage unit 220 storestime information indicating the time at which reading is performed inassociation with each key address used in the first search control orthe second search control. More specific details of the second storageunit 220 will be described later.

In a case where the size of value data to be written is smaller than athreshold, the aforementioned write control unit 212 selects a keyaddress used for searching within a predetermined time period beforewriting of the value data to be written is requested from among keyaddresses stored in the second storage unit 220 and adds the selectedkey address to the value data to be written.

More specific details are as follows. FIG. 10 is a block diagramillustrating an exemplary functional configuration of the second storageunit 220 according to the second embodiment, in which only the partrelating to the search function is illustrated. As illustrated in FIG.10, the second storage unit 220 includes a fifth storage unit 230 and asixth storage unit 240. The fifth storage unit 230 stores timeinformation indicating the time at which reading is performed accordingto the first search control in association with each key address used inthe first search control. The sixth storage unit 240 stores data readout according to the second search control and time informationindicating the time at which reading is performed according to thesecond search control in association with each key address used in thesecond search control. In a case where the size of the value data to bewritten is smaller than the threshold, the second write control unit 212then selects a key address associated with time information indicatingtime within the predetermined time period from among key addressesstored in the fifth storage unit 230 and the sixth storage unit 240 andadds the selected key address to the data. Alternatively, a mode inwhich a key address contained in search cache data read ahead (a keyaddress stored in the sixth storage unit 240), for example, is not addedto the value data to be written having a size smaller than the thresholdmay be applied.

Next, an example of control performed by the second write control unit212 will be described with reference to FIG. 11. FIG. 11 is a flowchartillustrating an example of the control performed by the second writecontrol unit 212. In this example, description will be made on theassumption that a key-value write request from the host device 200 isreceived by the receiving unit 211. As illustrated in FIG. 11, thesecond write control unit 212 checks whether or not the size of data(value data to be written) contained in the key-value write requestreceived by the receiving unit 211 is smaller than the threshold (stepS30). In this example, the second write control unit 212 checks whetheror not the proportion of the value data to be written in a page issmaller than 50%. If it is determined that the size of the value data tobe written is equal to or larger than the threshold (step S30: NO), theprocess proceeds to step S35, which will be described later.

If it is determine in step S30 that the size of the value data to bewritten is smaller than the threshold (step S30: YES), the second writecontrol unit 212 calculates the size of the empty area (step S31).Subsequently, the second write control unit 212 checks whether or notthe calculated size of the empty area is equal to or larger than athreshold (step S32). This threshold is set to a value allowingdetermination on whether or not the size of an empty area is equal to orlarger than the size of at least one key address. If it is determinedthat the calculated size of the empty area is smaller than the threshold(step S32: NO), the process proceeds to step S35, which will bedescribed later.

If, on the other hand, it is determined that the calculated size of theempty area is equal to or larger than the threshold (step S32: YES), thesecond write control unit 212 obtains (selects) a key address associatedwith time information indicating time within the predetermined timeperiod from among key addresses stored in the second storage unit 220(step S33).

Subsequently, the second write control unit 212 adds the one or more keyaddresses selected in step S33 to the value data to be written (stepS34). Subsequently, the second write control unit 212 appends a keyaddress obtained by converting a key contained in the key-value writerequest received by the receiving unit 211 and an offset allowing thedata length of the value data to be written to be obtained into theredundant part (step S35). Subsequently, the second write control unit102 generates a write command instructing the memory controller 250 toperform writing, adds information on which second write control is to beperformed and a physical address indicating the position in the firststorage unit 120 at which the value data to be written is to be writtento the generated write command, and transmits the write command to thememory controller 250 (step S36). The memory controller 250 in receiptof the write command from the second write control unit 212 then writesthe information into the first storage unit 120 according to thereceived write command.

Subsequently, the second write control unit 212 updates the K2P table(step S37). In the second embodiment, the second write control unit 212performs control of newly adding the key address obtained by convertingthe key contained in the key-value write request received by thereceiving unit 211 and the physical address indicating the position inthe first storage unit 120 into which the value data to be written iswritten in association with each other to the K2P table as describedabove.

Next, an example of control performed by the search control unit 213will be described with reference to FIG. 12. FIG. 12 is a flowchartillustrating an example of the control performed by the search controlunit 213. In this example, description will be made on the assumptionthat a set operation condition for narrowing search results is receivedtogether with a plurality of search requests from the host device 200.As illustrated in FIG. 12, the search control unit 213 first checkswhether or not search cache data containing a key address obtained byconverting a key contained in a search request is stored in the secondstorage unit 220 (the sixth storage unit 240) (step S40).

If it is determined in step S40 that the search cache data containingthe key address obtained by converting the key contained in the searchrequest is stored in the second storage unit 220 (step S40: YES), thesearch control unit 213 reads out data contained in the search cachedata from the second storage unit 220. Here, if a set operationcondition is not received by the receiving unit 211 (that is, in a caseof a single search request), the search control unit 213 transmits thedata read out from the second storage unit 220 as a response to thesearch request to the host device 200 and ends the process. Since,however, it is assumed in this example that a set operation condition isreceived by the receiving unit 211 together with a plurality of searchrequests, the process proceeds to step S45, which will be describedlater.

If, on the other hand, it is determined in step S40 that no search cachedata containing the key address obtained by converting the key containedin the search request is stored in the second storage unit 220 (stepS40: NO), the process proceeds to step S41. In step S41, the searchcontrol unit 213 refers to the K2P table to identify the physicaladdress associated with the key address obtained by converting the keycontained in the search request (step S41). Subsequently, the searchcontrol unit 213 generates a search command to instruct the memorycontroller 250 to perform a search, adds the physical address identifiedin step S41 to the generated search command, and transmits the searchcommand to the memory controller 250 (step S42). The memory controller250 in receipt of the search command reads out information from thefirst storage unit 120 and transmits the read information to the searchcontrol unit 213 according to the received search command. Thus, thesearch control unit 213 receives the information read out by the memorycontroller 250 as a response to the search command (step S43).

The processing in steps S41 to S43 corresponds to the first searchcontrol. Subsequently, the search control unit 213 refers to the offsetcontained in the information read out according to the first searchcontrol of checking whether or not the data length is smaller than thethreshold (step S44). If no set operation condition is received by thereceiving unit 211 (in the case of a single search request), and if itis determined that the data length is equal to or larger than thethreshold (step S44: NO), the search control unit 213 transmits datacontained in the information read out according to the first searchcontrol to the host device 200 as a response to the search request, andends the process. Since, however, it is assumed in this example that aset operation condition is received by the receiving unit 211 togetherwith a plurality of search requests, the process proceeds to step S45.In step S45, the search control unit 213 performs set operation on a setof data contained in the information read out by using the key addressesobtained by converting keys in the respective search requests accordingto the received set operation condition to narrow the search results.The search control unit 213 then transmits the search results narrowedby the set operation to the host device 200 as a response to the searchrequests (step S46), and ends the process.

If, on the other hand, it is determined in step S44 that the data lengthis smaller than the threshold (step S44: YES), the search control unit213 obtains a key address added to the data in writing from the partother than the data and the redundant part of the information read outaccording to the first search control (step S47). In the presentembodiment, the search control unit 213 may also perform the processingin step S45 (set operation) by using the data smaller than the thresholdcontained in the information read out according to the first searchcontrol in parallel with the processing in step S47. If no set operationcondition is received by the receiving unit 211 (in the case of a singlesearch request), for example, the search control unit 213 transmits datasmaller than the threshold contained in the information read outaccording to the first search control to the host device 200 as aresponse to the search request, and ends the process.

Subsequently, the search control unit 213 refers to the K2P table toidentify the physical address associated with each of the one or morekey addresses obtained in step S47 (step S48). Subsequently, the searchcontrol unit 213 generates a search command to instruct the memorycontroller 250 to perform a search, adds the physical address identifiedin step S48 to the generated search command, and transmits the searchcommand to the memory controller 250 (step S49). The memory controller250 in receipt of the search command reads out information from thefirst storage unit 120 and transmits the read information to the searchcontrol unit 213 according to the received search command. Thus, thesearch control unit 213 receives the information read out by the memorycontroller 250 as a response to the search command (step S50).

The processing in steps S47 to S50 corresponds to the second searchcontrol. After step S50, the search control unit 213 then performscontrol of storing the data contained in the information received fromthe memory controller 250 (the information read out according to thesecond search control) and the key address in association with eachother into the second storage unit 220 (the sixth storage unit 240)(step S51). As a result, cache data read ahead is newly added to thesixth storage unit 240.

The programs to be executed by the device controller (112, 210)according to the embodiments described above may be stored on a computersystem connected to a network such as the Internet, and provided bybeing downloaded via the network. Alternatively, the programs to beexecuted by the device controller (112, 210) according to theembodiments described above may be provided or distributed through anetwork such as the Internet. Still alternatively, the programs to beexecuted by the device controller (112, 210) according to theembodiments described above may be embedded on a nonvolatile recordingmedium such as a ROM or the like in advance and provided therefrom.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1.-12. (canceled)
 13. A storage device, comprising: a first storageconfigured to store first data from a host device; a second storageconfigured to store a logical address for reading the first data in thefirst storage; and a controller configured to, when a size of first datarequested to be written into the first storage by the host device issmaller than a threshold, perform control of generating second data byadding the logical address to the first data and control of writing thesecond data into the first storage.
 14. The device according to claim13, further comprising: a receiver configured to receive a read requestfor requesting to read first data from the host device; a readcontroller configured to, when the receiver receives the read request,refer to logical-to-physical translation information indicative of anassociation between a physical address indicative of a position in thefirst storage and a logical address to identify a physical addressassociated with a logical address contained in the read request, andperform first read control of reading out information stored at aposition indicated by an identified physical address.
 15. The deviceaccording to claim 14, wherein: the read controller is configured to,when a logical address is contained in information read out according tothe first read control, perform second read control of reading outinformation stored at a position indicated by a physical addressassociated with the logical address, and the read controller isconfigured to perform control of storing first data contained ininformation read out according to the second read control and thelogical address in association with each other into the second storage.16. The device according to claim 15, wherein the read controller isconfigured to, when a logical address matching the logical addresscontained in the read request received by the receiver and first dataare stored in association with each other in the second storage, performthird read control of reading out first data associated with a logicaladdress matching the logical address contained in the read request fromthe second storage.
 17. The device according to claim 14, wherein theread controller is configured to perform control of storing at least alogical address used in the first read control into the second storageeach time the read controller performs the first read control.
 18. Thedevice according to claim 17, wherein the controller is configured to,when a size of first data requested to be written is smaller than thethreshold, select a logical address used for reading within apredetermined time period before the first data is requested to bewritten from among logical addresses stored in the second storage andgenerate second data by adding a selected logical address to the firstdata.
 19. The device according to claim 18, wherein the second storageis configured to store time information indicative of time at whichreading of information from the first storage is performed inassociation with each logical address, and the controller is configuredto, when a size of first data requested to be written is smaller thanthe threshold, select a logical address associated with time informationindicative of time contained in the predetermined time period from amongthe logical addresses stored in the second storage and generate seconddata by adding a selected logical address to the first data.
 20. Thedevice according to claim 19, wherein: the second storage includes: athird storage configured to store a logical address used in the firstread control and the time information indicative of time at whichreading according to the first read control is performed in associationwith each other; and a fourth storage configured to store a logicaladdress used in the second read control, first data read out accordingto the second read control, and time information indicative of time atwhich reading according to the second reading control is performed inassociation with one another, and the controller is configured to, whena size of first data requested to be written is smaller than thethreshold, select a logical address associated with time informationindicative of time within the predetermined time period from amonglogical addresses stored in the third storage and the fourth storage andgenerate second data by adding a selected logical address to first datarequested to be written.
 21. The device according to claim 20, whereinthe third storage is a FIFO memory.
 22. The device according to claim19, wherein: the second storage includes a third storage configured tostore a logical address used in the first read control and timeinformation indicative of time at which reading according to the firstread control is performed in association with each other; and a fourthstorage configured to store a logical address used in the second readcontrol and first data read out according to the second read control inassociation with each other, and the controller is configured to, when asize of first data requested to be written is smaller than thethreshold, select a logical address associated with time informationindicative of time within the predetermined time period from amonglogical addresses stored in the third storage and generate second databy adding a selected logical address to first data requested to bewritten.
 23. The device according to claim 22, wherein the third storageis a FIFO memory.
 24. A storage device, comprising: a first storageconfigured to store first data from a host device; a second storageconfigured to store a key address for searching first data associatedwith a key specified by the host device; and a controller configured to,when a size of first data requested to be written into the first storageby the host device is smaller than a threshold, perform control ofgenerating second data by adding a key address stored in the secondstorage to the first data and writing generated second data into thefirst storage.